The present invention relates to the processing of semiconductor substrates, in particular how to prepare semiconductor wafers for processing. The present invention particularly relates to the manufacture of integrated circuits, for example as a xe2x80x9cchipxe2x80x9d.
Silicon wafer sizes used in the semiconductor industry are nowadays 100 mm in diameter minimum. The conversion of the present semiconductor industry from 200 mm to 300 mm diameter silicon wafers is a new challenge for chip manufacturers. The main motivation for the conversion to larger wafer sizes is the fact that more chips may be produced using the same effort in skilled manpower and resources. A possible reduction in cost per function (by technology improvements or by reduction of manufacturing costs) is a basic driving force for the microelectronics industry. Currently, reduction of costs can be obtained by increased equipment productivity, reduction in start-up time of fabs, reduction in queue time and using cost of ownership principles. Increasing the wafer size, may well have a negative impact on these possible cost reductions. When changing the wafer size, most effort and money will be spent on making sure the wafer is processed uniformly, to keep the throughput of chips high. Less money is available for secondary equipment and manufacturing improvements. However, lithographic steps are the most expensive steps in IC manufacturing. The throughput of this step determines the overall throughput of the IC manufacturing line and manufacturing cost.
U.S. Pat. No. 4,810,616 describes a work holder for holding a plurality of ceramic pieces. Each ceramic piece may be used for holding one integrated circuit. The holder is designed so that conductive wiring may be applied to the ceramic pieces. Each ceramic piece is held in place by a metallic spring. The work holder may also be made of metal. This type of work holder and piece fixing method cannot be used in the processing of integrated circuits and is remote from the present invention. The known holder would generate considerable amounts of contamination in the finished IC""s through contact diffusion from the metal spring and/or work holder into the active devices of the IC when carrying out a thermal treatment step at 450xc2x0 C. or above, e.g. during CVD deposition of dielectrics, annealing after implant of doping, epitaxy deposition of layers, silicidation, oxidation, nitridation. At least one of these processes is essential in the manufacture of an IC. Information about contamination and how to prevent it may be obtained from xe2x80x9cUltra-clean surface processing of silicon wafers,xe2x80x9d by Takeshi Hattori, Springer Verlag, 1998.
The object of the invention is to present a new basic concept for chip manufacturing which provides an answer to the current economic challenges for chip manufacturers.
It is a further object of the present invention to provide a method and apparatus for manufacturing integrated circuits which are more economic and more easily optimized.
The present invention includes a semiconductor processing system for the production of semiconductor electronic devices, which includes a sequence of semiconductor processing steps carried out on a plurality of semiconductor processing machines, whereby the processing is carried out on discrete pieces of semiconductor substrate which are smaller than the conventional diameter of semiconductor wafers but may be made therefrom, or from larger wafers or from materials onto which semiconductor layers may be formed, and the discrete substrate pieces are selectably processable into the electronic devices either individually or as a plurality, wherein at least one of the semiconductor processing steps comprises a thermal treatment step at a temperature of 450xc2x0 C. or above in which diffusing contamination is a critical factor with respect to the quality of the electronic devices produced, and the discrete substrate pieces are fixed to a support suitable for the above thermal treatment step, the discrete substrate pieces being separable from each other after processing. The relevant contamination may include organic or inorganic contamination in the form of any of particle contamination, gaseous contamination or solid contact contamination (diffusion contamination from contact with solids such as metals). The thermal treatment step may be one of the non-limiting list of: CVD deposition of dielectrics, annealing after implant of doping, epitaxy deposition of layers, silicidation, oxidation, nitridation. The discrete pieces as fixed to the support are preferably arranged in an a planar array. The discrete pieces are preferably polygonal in shape. The discrete pieces are preferably fixed to the support in such a way that they are surrounded by a substantially uniform thermal environment. Particularly preferred are fixing methods on which the complete surface of each discrete piece is in contact with a flat surface of the support. Also preferred are fixing methods in which at least a central area of the discrete piece is surrounded by a uniform thermal environment. In particular, it is preferred if the thermal resistance per unit area between at least the central area of each discrete piece and the support is substantially constant. The discrete pieces are preferably fixed to the support before loading into a processing machine and the discrete pieces are loaded and unloaded from at least one processing machine while being fixed to the support. The details of the support are given below. Preferably, the processing machines are semiconductor wafer processing machines. The conventional wafer diameters are 100 mm or more. At least one of the processing machines includes a lithographic machine and the dimensions of the discrete pieces of substrate may be related to the field of view of the lithographic machine, preferably the same as or larger than the field of view of the lithographic machines, e.g. a multiple thereof, typically twice or four times. The size, of each discrete piece may be chosen so that there are 10 steps or less in the lithographic machine for each discrete piece. The separation of the final electronic devices may be done by removing the pieces from the support or by dicing the support to isolate each electronic device without necessarily removing each piece from its surrounding support.
The present invention also includes a method for making a plurality of integrated circuits each including an active device, comprising the steps of: providing a plurality of semiconductor substrate pieces with predetermined dimensions; seperably fixing the plurality of substrate pieces on a support; and subjecting the plurality of substrate parts on the support to at least one process step of a sequence of process steps for producing the integrated circuits, the at least one process step comprising a thermal treatment step at a temperature of 450xc2x0 C. or above in which contamination is a critical factor with respect to the quality of the active devices produced. Some of the process steps for chip manufacturing are applied to the support with its pieces of substrate rather than to a conventional type of wafer. Typical processes may be one of the non-limiting list of: CVD deposition of dielectrics, annealing after implant of doping, epitaxy deposition of layers, silicidation, oxidation, nitridation. The relevant contamination may include organic or inorganic contamination in the form of any of particle contamination, gaseous contamination or solid contact contamination (diffusion contamination from contact with solids such as metals).
An embodiment of the present invention is that the part of substrate is cut from a silicon wafer as grown. An embodiment of the present invention is that the part of substrate is cut from a silicon wafer which is thinned before cutting. An embodiment of the present invention is that the predetermined dimensions of the part of substrate are equal to the chip size or a multiple thereof. An embodiment of the present invention is that the predetermined dimensions of the part of pieces substrate are determined by the field of view of the optical lithography tools used in chip manufacturing. An embodiment of the present invention is that the predetermined dimensions of the substrate pieces are determined such that the throughput of chips in the manufacturing process is optimized.
The present invention also includes a support for holding a plurality of discrete substrate parts to be processed into integrated circuits, comprising: a plurality of locations on the support, each for one discrete substrate part; and means holding each substrate part at each location, such that the surface of the substrate part projects from the surface of the support by a distance within a predetermined range, the holding means and the support being thermally and chemically compatible with the substrate parts and at least one processing step for manufacture of the integrated circuits, the at least one process step comprising a thermal treatment step at a temperature of 450xc2x0 C. or above in which contamination is a critical factor with respect to the quality of the integrated circuits produced. The relevant contamination may include organic or inorganic contamination in the form of any of particle contamination, gaseous contamination or solid contact contamination (diffusion contamination from contact with solids such as metals). The material of the support is preferably compatible with all integrated circuit manufacturing steps. In the support, recesses may be provided into which fit the pieces of substrate. The positioning of the pieces of substrate is preferably such that these project from the support and the height of the surface of the pieces (defined with respect to the surface of the support) is within a predefined range. An embodiment of the present invention is that the material of the pieces of substrate and the material of the support are thermally compatible, thus chosen such that during the processing at elevated temperature (higher than 450xc2x0 C.) only a minimal of thermal stress is placed on the pieces of substrate. An embodiment of the present invention is that the predefined range for the height of the surface of the pieces of substrate with respect to the surface of the support is determined by the planarization requirements for manufacturing integrated circuit. As such the range is determined by limitations imposed by polishing and the lithographic tools used in the manufacturing of integrated circuits. An embodiment of the present invention is that the fixing of the substrate pieces on the support is done by positioning the substrate pieces in individual recesses in the support and then depositing a layer on the support, thus restraining the substrate pieces and finally the layer is removed from the surface of that part of the substrate pieces in which the integrated circuit will be made. An embodiment of the present invention includes the fixing of the substrate pieces on the support by positioning the substrate pieces in individual ones of the recesses on the support and then melting at least a part of the border of the substrate pieces. An embodiment of the present invention is the fixing of the substrate pieces on the support by adhesive or cement. The separation of the final integrated circuits may be done by removing the pieces from the support or by dicing the support to isolate each electronic device without necessarily removing each piece from its surrounding support.
The dependent claims define individually further embodiments of the present invention. The present invention will now be described with reference to the following drawings.